1. Technical Field of the Invention
The present invention generally relates to integrated circuits (“ICs”). More particularly, and not by way of any limitation, the present invention is directed to a method and apparatus for facilitating the implementation of multiple remote diagnose register chains in an IC.
2. Description of Related Art
As the size of integrated circuits (“ICs”) continues to shrink while the number of elements included thereon continues to grow, testing such circuits has become increasingly difficult. To ensure the accuracy with which testing can be performed on such circuits, diagnostic testing circuitry can be built into an IC. In one embodiment, data may be serially transferred to or from a staging register through a plurality of shift register stages positioned at various locations throughout the IC. In this manner, circuit testing of the IC can be quickly and accurately conducted.
FIG. 1A illustrates an implementation of a remote diagnose register chain 100 in accordance with the prior art. The chain 100 comprises a staging register 102 and multiple remote diagnose registers (“RDRs”), respectively designated in FIG. 1A by reference numerals 104(0)–104(n-1) all connected in series, with the output of each register 102, 104(0)–104(n-1), in the chain 100 being connected to the input of the next register in the chain. The staging register 102 and each of the RDRs 104(0)–104(n-1) are conventional 64-bit serial shift registers.
In a typical implementation, for reasons that will be described in greater detail below, the chain is limited to 32 RDRs. Accordingly, n is also limited to 32. As will also be described below, during a write operation, data is serially shifted under appropriate control logic, one bit at a time, out of the staging register 102 and along the chain 100 in a single direction (which in the illustrated embodiment is clockwise) until it reaches a designated one of the RDRs 104(0)–104 (n-1), at which point it is written into that RDR.
During a read operation, data is serially shifted, again one bit at a time, from a designated one of the RDRs 104(0)–104(n-1) along the chain in the same direction as previously described until it reaches the staging register 102, at which point, it is written into the staging register.
The embodiment illustrated in FIG. 1A functions adequately for an IC that includes a single processor core; however, in most applications, a single core utilizes almost all of the 32 RDRs. Accordingly, as complexity has increased and more processor cores, as well as shared functional units, are included on a single die, more RDRs for use as configuration and error logging registers are needed. However, as previously alluded to, current standards, which provide for designation of a particular RDR within a chain by a five-bit number, limit the number of RDRs included in an RDR chain to 32 registers.
Additionally, there is currently no method of handling a situation in which all cores need to be able to access the same shared data.